Systematic process variation analysis of single-mode silicon waveguides and grating couplers during dry etching

LIU Yongkang; ZHANG Yimeng; BAO Xiaoqing; DAI Daiqiang; WANG Shuming

doi:10.37188/OPE.20263415.2378

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Systematic process variation analysis of single-mode silicon waveguides and grating couplers during dry etching

Micro\/Nano Technology and Fine Mechanics | 更新时间：2026-08-20

- Systematic process variation analysis of single-mode silicon waveguides and grating couplers during dry etching
- Optics and Precision Engineering Vol. 34, Issue 15, Pages: 2378-2388(2026)
- 作者机构：
  
  1.安徽建筑大学电子与信息工程学院，安徽合肥 230000
  2.南京信息工程大学环境气象集成芯片与系统江苏省产业技术工程化中心，江苏南京 210044
  3.南京南智先进光电集成技术研究院，江苏南京 211800
  4.南京大学固体微结构物理国家重点实验室，江苏南京 211800
- 作者简介：
- 基金信息：
- DOI：10.37188/OPE.20263415.2378
  CLC： TN305.7;TH162+.1
- CSTR：32169.14.OPE.20263415.2378
- Received：05 June 2026，
  
  Revised：2026-06-26，
  
  Online First：14 August 2026，
  
  Published：10 August 2026
- 稿件说明：
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刘永康,张怡梦,包晓清等.单模硅波导与光栅耦合器在干法刻蚀中的系统性工艺偏差分析[J].光学精密工程,2026,34(15):2378-2388.

LIU Yongkang,ZHANG Yimeng,BAO Xiaoqing,et al.Systematic process variation analysis of single-mode silicon waveguides and grating couplers during dry etching[J].Optics and Precision Engineering,2026,34(15):2378-2388.
刘永康,张怡梦,包晓清等.单模硅波导与光栅耦合器在干法刻蚀中的系统性工艺偏差分析[J].光学精密工程,2026,34(15):2378-2388. DOI： 10.37188/OPE.20263415.2378. CSTR： 32169.14.OPE.20263415.2378.

LIU Yongkang,ZHANG Yimeng,BAO Xiaoqing,et al.Systematic process variation analysis of single-mode silicon waveguides and grating couplers during dry etching[J].Optics and Precision Engineering,2026,34(15):2378-2388. DOI： 10.37188/OPE.20263415.2378. CSTR： 32169.14.OPE.20263415.2378.

摘要

本研究系统评估了8英寸绝缘层上硅平台光刻与干法刻蚀工艺的晶圆级均匀性对硅光无源器件物理形貌及光学性能的映射关系。基于220 nm顶层硅平台，采用深紫外光刻与电感耦合等离子体反应离子刻蚀工艺，完成了光栅耦合器（70 nm 浅刻蚀）与单模直波导（220 nm 全刻蚀）的两步全流程流片加工。利用原子力显微镜、关键尺寸扫描电子显微镜及全自动光学探针台对5片8寸晶圆的物理尺寸与传输损耗进行了全片表征。结果表明，不同晶圆间的平均刻蚀深度和平均线宽保持在相对稳定范围内；然而，在单片晶圆内部观察到一定的径向工艺偏差，这种边缘区域的微观尺寸缩减及侧壁形貌退化可能会影响光模场分布，并增加侧壁散射损耗，最终使得单模波导的传输损耗呈现出从中心区域向边缘区域升高的趋势。综上所述，大尺寸晶圆干法刻蚀过程中可能存在的宏观负载效应与侧向刻蚀行为是影响硅光芯片片内性能一致性的重要因素之一，该发现为未来在8英寸SOI平台上进行光学邻近效应补偿、刻蚀配方优化及晶圆级良率提升提供了实验参考和工艺优化依据。

Abstract

This study aims to systematically investigate the mapping relationship between wafer-level uniformity in lithography and dry etching processes， and the physical morphology and optical performance of silicon photonic passive devices on an 8-inch silicon-on-insulator （SOI） platform. The experiments were conducted on a 220 nm top-silicon SOI platform. A two-step full-process fabrication flow was implemented using deep ultraviolet （DUV） lithography and inductively coupled plasma reactive ion etching （ICP-RIE）. The process included the fabrication of grating couplers with a 70 nm shallow etch and single-mode straight waveguides with a 220 nm full etch. The physical dimensions and optical propagation loss were systematically characterized across five 8-inch wafers using atomic force microscopy （AFM）， critical-dimension scanning electron microscopy （CD-SEM）， and an automated optical probe station. A certain degree of wafer-to-wafer stability was observed among the five wafers. Statistical analysis based on standard deviation， semi-range， and their relative variations indicated that the average etch depth and average linewidth remained within relatively stable ranges across different wafers. However， within-wafer （WIW） radial process variations were observed. The reduction in microscopic dimensions in the edge region， together with possible sidewall morphology degradation， may alter the optical mode distribution and increase sidewall scattering loss. As a result， the propagation loss of the single-mode waveguides exhibited an increasing trend from the wafer center toward the edge. These results suggest that macro-loading effects and lateral etching behavior during dry etching of large-diameter wafers are important factors influencing within-wafer performance consistency in silicon photonic chips. The findings provide experimental evidence and process optimization guidance for future optical proximity correction （OPC）， etching recipe optimization， and wafer-level yield improvement on 8-inch SOI platforms.

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