Interface design for high-speed digital CCD camera

based on VHDL description

was presented. The interface circuit was made of Lattice 1k series CPLD(Complex Programmable Logic Device). As VHDL and CPLD were used incorporately

some circuit functions traditionally provided by hardware would be involved with software for more flexibility. Designer could modify the design while the circuits were running. Some codes with VHDL for interface circuit were given. VHDL logic synthesis was used to solve the problem of optimum design. Timing simulation of circuit was proposed and simulation results were shown. Synthesizability problems of VHDL design are analyzed and studied.