In order to solve the problem that the VLSI architecture of discrete wavelet transform wastes a huge amount of hardware resources

we propose a parallel VLSI architecture of discrete wavelet transform for JPEG2000. The architecture introduces (9

7) wavelet parallel filtering technique based on the time difference

so that the row processor and the column processor can process the signals in parallel way. The 2×2 transforming module makes it true that several registers substitute a lot of medium transforming memory. Experimental results show that the proposed architecture

under the tight critical path

can efficiently decrease the hardware complexity and achieve hardware utilization nearly 100%. Finally

the architecture has been implemented in post-route VHDL

and can be used as a compact and independent IP core for VDR radar image acquisition card.