Optimization of bandwidth for phase-locked loop in OTU

YUAN Jian-guo; LI Hao; He Qing-ping

doi:10.3788/OPE.20111908.1937

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Optimization of bandwidth for phase-locked loop in OTU

Article | 更新时间：2020-08-12

- Optimization of bandwidth for phase-locked loop in OTU
- Optics and Precision Engineering Vol. 19, Issue 8, Pages: 1937-1943(2011)
- 作者机构：
  
  重庆邮电大学光纤通信技术重点实验室重庆,400065
- 作者简介：
- 基金信息：
- DOI：10.3788/OPE.20111908.1937
  CLC： TN929.53
- Received：13 December 2010，
  
  Revised：15 February 2011，
  
  Published Online：25 August 2011，
  
  Published：25 August 2011
- 稿件说明：
移动端阅览
袁建国, 李好, 何清萍. 光转换单元中锁相环带宽的优化[J]. 光学精密工程, 2011,19(8): 1937-1943

YUAN Jian-guo, LI Hao, He Qing-ping. Optimization of bandwidth for phase-locked loop in OTU[J]. Editorial Office of Optics and Precision Engineering, 2011,19(8): 1937-1943
袁建国, 李好, 何清萍. 光转换单元中锁相环带宽的优化[J]. 光学精密工程, 2011,19(8): 1937-1943 DOI： 10.3788/OPE.20111908.1937.

YUAN Jian-guo, LI Hao, He Qing-ping. Optimization of bandwidth for phase-locked loop in OTU[J]. Editorial Office of Optics and Precision Engineering, 2011,19(8): 1937-1943 DOI： 10.3788/OPE.20111908.1937.

摘要

考虑光转换单元(OTU)中锁相环带宽同时受外部输入抖动和内部相位噪声抖动的影响

为克服锁相环带宽选择的矛盾性

本文对其带宽进行了优化设计。在同时考虑外部输入抖动和内部相位噪声的情况下

对锁相环带宽算法进行综合分析。通过改进前人的计算和分析方法推导得出OTU中锁相环带宽的优化算法

分析并得到锁相环路的优化带宽

使OTU的时钟输出有较低的抖动噪声。将优化算法应用到2.5 Gbit/s和10 Gbit/s的OTU中

对环路参数进行定量和定性分析

获得了锁相环的优化参数和再生器输出抖动值。实验研究表明

该优化算法具有一定优越性与可行性

比较适用于OTU。

Abstract

As both the external input jitter and the internal phase noise jitter impact on the bandwidth of Phase-Locked Loop(PLL) in an Optical Transponder Unit(OTU)

the bandwidth of the PLL was designed optimally to solve the contradiction of the wavelength selection. With consideration of the external input jitter and the internal phase noise

the bandwidth algorithm of the PLL was comprehensively analyzed

and an optimization algorithm of the bandwidth for PLL in the OTU was deduced through improving calculation and analytical methods from formers. The optimal bandwidth of the PLL can ensure the lower jitter noise of clock output in the OUT. The optimization algorithm was applied in the OTUs with 2.5 Gbit/s and 10 Gbit/s

respectively to analyze the loop parameters and the optimal parameters of the PLL and the output jitter value of a regenerator were acquired quantitatively and qualitatively. The experiment shows that the optimization algorithm is superior to traditional algorithms and more suitable for OTUs.

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Keywords

references

王龙水, 李勇. 光传输网的抖动和漂移[M]. 北京:北京邮电大学出版社, 2002. WANG L SH, LI Y. The Jitter and Wander in Optical Transmission Network[M]. Beijing: Press of Beijing University of Posts and Telecommunications, 2002.[2] GURUMOORTHY V,PALERMO S. Supply regulation techniques for phase-locked loops .Circuits and Systems Workshop(DCAS 2009), Dallas IEEE,2009:1-4.[3] van der TANG J D, VAUCHER C S. Design and optimization of a low jitter clock-conversion PLL for SONET/SDH optical transmitters .Electronics, Circuits and Systems(ICECS 2001), Poland Zakopane, IEEE,2001:31-34.[4] 张厥盛, 郑继禹,万心平. 锁相环技术[M]. 西安:西安电子科技大学出版社, 2003. ZHANG J SH, ZHENG J Y,WAN X P. Phase-Locked Loop Technologies[M]. Xian: Press of Xidian University, 2003.(in Chinese)[5] KYOOHYUN L, PARK CH H, KIM D,et al.. A low-noise phase-locked loop design by loop bandwidth optimization[J]. IEEE Journal of Solid-State Circuits, 2000,35(6):807-815.[6] KROUPA V F. Phase Lock Loops and Frequency Synthesis[M]. West Sussex England: John Wiley & Sons Ltd, 2003.[7] XIANG G, KLUMPERINK E A M, GERAEDTS P F J, et al.. Jitter analysis and a benchmarking figure-of-merit for phase-locked loops[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2009,56(2):117-121.[8] KHO J, LOH C I, WUI H M, et al.. Extended analysis of SSN effect on phase-locked loop (PLL) circuit .Electrical Design of Advanced Packaging & Systems Symposium(EDAPS 2009). Hong Kong, IEEE, 2009: 1- 4.[9] PEDRO R, JOSEP P, JOAN B, et al.. Decoupled double synchronous reference frame PLL for power converters control[J]. IEEE Trans. on Power Electronics, 2007,22(2):584-592.[10] KAMATH A S, CHATTOPADHYAY B A. 13 MHz input, 480 MHz output Fractional Phase Lock Loop with 1 MHz bandwidth .Circuits and Systems (ISCAS 2010), Paris IEEE,2010:501-504.[11] ARAKALI A,GONDI S,HANUMOLU P K. Analysis and design techniques for supply-noise mitigation in phase-locked loops[J]. IEEE Journal of Circuits and Systems I, 2010, 57(11):2880-2889.

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