Design of quadrature 2∶1 frequency divider for GNSS receivers

YIN Xi-zhen; YU Yun-feng; MA Cheng-yan; YE Tian-chun

doi:10.3788/OPE.20122005.1015

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Design of quadrature 2∶1 frequency divider for GNSS receivers

Article | 更新时间：2020-08-12

- Design of quadrature 2∶1 frequency divider for GNSS receivers
- Optics and Precision Engineering Vol. 20, Issue 5, Pages: 1015-1021(2012)
- 作者机构：
  
  1. 中国科学院微电子研究所, 北京 100029
  2. 杭州中科微电子有限公司, 浙江杭州310053
- 作者简介：
- 基金信息：
- DOI：10.3788/OPE.20122005.1015
  CLC： TN772
- Received：18 January 2012，
  
  Revised：10 February 2012，
  
  Published Online：10 May 2012，
  
  Published：10 May 2012
- 稿件说明：
移动端阅览
尹喜珍, 于云丰, 马成炎, 叶甜春. 全球卫星导航系统接收机的正交二分频器设计[J]. 光学精密工程, 2012,20(5): 1015-1021

YIN Xi-zhen, YU Yun-feng, MA Cheng-yan, YE Tian-chun. Design of quadrature 2∶1 frequency divider for GNSS receivers[J]. Editorial Office of Optics and Precision Engineering, 2012,20(5): 1015-1021
尹喜珍, 于云丰, 马成炎, 叶甜春. 全球卫星导航系统接收机的正交二分频器设计[J]. 光学精密工程, 2012,20(5): 1015-1021 DOI： 10.3788/OPE.20122005.1015.

YIN Xi-zhen, YU Yun-feng, MA Cheng-yan, YE Tian-chun. Design of quadrature 2∶1 frequency divider for GNSS receivers[J]. Editorial Office of Optics and Precision Engineering, 2012,20(5): 1015-1021 DOI： 10.3788/OPE.20122005.1015.

摘要

将全球卫星导航系统(GNSS)接收机用于手持移动设备必须降低正交二分频器等大功耗模块的功耗

因此

本文提出了工作于1 V电压以下的正交二分频器。使用提出的正交二分频器可使电路在各工艺角下高速稳定的工作

并大大降低模块的功耗。首先

介绍已有的高速二分频器。接着

计算了所提出结构的直流静态偏置

并对提出的锁存器进行小信号建模和分析。最后

根据小信号模型分析得到的条件和GNSS接收机的应用要求

设计了提出的低功耗结构。实验结果表明:提出的二分频器最高工作频率为6.55 GHz

最低可工作到0.25 GHz

消耗电流为0.8 mA

占用面积为0.014 4 mm

。提出的电路结构在0.13 m CMOS工艺上实现

可稳定工作于1 V电压下

目前已成功应用于低功耗的移动GNSS接收机中。

Abstract

When the Global Navigation Satellite System (GNSS) receivers are applied to a portable handset

the power of the most power-hungry blocks

such as quadrature 2∶1 frequency divider

should be reduced. Therefore

this paper proposes a 1 V low power quadrature 2∶1 frequency divider at high speed and steady working in all process corners. First

the published high speed architectures are introduced. Then the static DC bias is calculated for the proposed architecture

and a small signal model for proposed flip-flop is developed and analyzed. Finally

a low power circuit is designed according to the analysis conditions of small signal model and the application requirements of GNSS receivers. Experimental results indicate that the proposed frequency divider works from 6.55 to 0.25 GHz

its consume current is only 0.8 mA

and the core area is 0.014 4 mm

. The proposed quadrature 2∶1 frequency divider is implemented in a 0.13 m CMOS process

and can steadily work in a sub 1 V supply voltage. It has been successfully applied to low power portable GNSS receivers.

关键词

Keywords

references

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Department of Photo-electronic Engineering, School of Information Science and Technology, Beijing Institute of Technology

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