Manufacture of low-g micro inertial switch utilizing SOI with double buried layers

WANG Chao; WU Jia-li; CHEN Guang-yan

doi:10.3788/OPE.20122005.1076

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Manufacture of low-g micro inertial switch utilizing SOI with double buried layers

Article | 更新时间：2020-08-12

- Manufacture of low-g micro inertial switch utilizing SOI with double buried layers
- Optics and Precision Engineering Vol. 20, Issue 5, Pages: 1076-1083(2012)
- 作者机构：
  
  中国工程物理研究院电子工程研究所,四川绵阳,621900
- 作者简介：
- 基金信息：
- DOI：10.3788/OPE.20122005.1076
  CLC： TM564;TN305
- Received：20 January 2012，
  
  Revised：15 February 2012，
  
  Published Online：10 May 2012，
  
  Published：10 May 2012
- 稿件说明：
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王超, 吴嘉丽, 陈光焱. 应用双埋层SOI工艺制备低g值微惯性开关[J]. 光学精密工程, 2012,20(5): 1076-1083

WANG Chao, WU Jia-li, CHEN Guang-yan. Manufacture of low-g micro inertial switch utilizing SOI with double buried layers[J]. Editorial Office of Optics and Precision Engineering, 2012,20(5): 1076-1083
王超, 吴嘉丽, 陈光焱. 应用双埋层SOI工艺制备低g值微惯性开关[J]. 光学精密工程, 2012,20(5): 1076-1083 DOI： 10.3788/OPE.20122005.1076.

WANG Chao, WU Jia-li, CHEN Guang-yan. Manufacture of low-g micro inertial switch utilizing SOI with double buried layers[J]. Editorial Office of Optics and Precision Engineering, 2012,20(5): 1076-1083 DOI： 10.3788/OPE.20122005.1076.

摘要

采用双埋层SOI(Silicon-On-Insulator)材料

结合KOH腐蚀工艺、电感耦合等离子体(ICP)刻蚀工艺、阳极键合以及喷雾式涂胶工艺

研制了一种基于平面矩形螺旋梁的低

值微惯性开关。利用二氧化硅KOH腐蚀/ICP刻蚀自停止的特点

平面矩形螺旋梁厚度的精度为0.46 m。分析了双埋层SOI材料的电学特性

采用等电位技术

实现了双埋层SOI与上下两层硼硅玻璃的阳极键合。采用玻璃无掩模湿法腐蚀技术

在玻璃封盖底部设计制作了大小为200 m200 m的防粘连凸台

解决了芯片在清洗干燥过程中的粘连问题。采用ICP刻蚀用硅衬片方法

解决了ICP刻蚀工艺中高温导致的金硅共晶合金问题。实验验证显示

提出的方法效果较好

芯片成品率得到较大提高

为大批量地研制低

值微惯性开关提供了可靠的工艺基础。

Abstract

A low-

micro inertial switch based on the planar rectangular helical spring was developed by utilizing a SOI (Silicon-On-Insulator) wafer with double buried layers and the manufacturing technology including KOH etching

Inductance Coupled Plasma (ICP) etching

anodic bonding and spray coating. Based on the self-stop technique for KOH etching and ICP etching of the buried layers

the precision of the spring thickness was controlled to be 0.46 m. The electrical property of the SOI wafer was analyzed. The anodic bonding between borosilicate glass and SOI wafer was successfully carried out utilizing the uniform electric potential technique

and an anti-stiction structure with a size about 200 m200 m was fabricated using the maskless pyrex-etching in the process of wafer cleaning and drying. Finally

a silicon-base was used to solve the Au-Si eutectic problem resulted from high temperature during ICP etching process. Experiments show that the chip yield is greatly increased by optimizing the fabrication process and the fabrication process can support the production of low-

micro inertial switches in batches.

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Keywords

references

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