Large capacity FLASH video storage controller base on blanking period of line and field signals

YANG Jin-bao; LI Fei; QIE Jun-wei

doi:10.3788/OPE.20152304.1153

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Large capacity FLASH video storage controller base on blanking period of line and field signals

更新时间：2020-08-13

- Large capacity FLASH video storage controller base on blanking period of line and field signals
- Optics and Precision Engineering Vol. 23, Issue 4, Pages: 1153-1160(2015)
- 作者机构：
  
  北京环境特性研究所光学辐射重点实验室北京,100854
- 作者简介：
- 基金信息：
- DOI：10.3788/OPE.20152304.1153
  CLC： TN941;TP333.5
- Received：28 November 2014，
  
  Revised：22 January 2015，
  
  Published：25 April 2015
- 稿件说明：
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杨金宝, 李飞, 郄军伟. 基于视频行场消隐期的大容量FLASH存储控制器[J]. 光学精密工程, 2015,23(4): 1153-1160

YANG Jin-bao, LI Fei, QIE Jun-wei. Large capacity FLASH video storage controller base on blanking period of line and field signals[J]. Editorial Office of Optics and Precision Engineering, 2015,23(4): 1153-1160
杨金宝, 李飞, 郄军伟. 基于视频行场消隐期的大容量FLASH存储控制器[J]. 光学精密工程, 2015,23(4): 1153-1160 DOI： 10.3788/OPE.20152304.1153.

YANG Jin-bao, LI Fei, QIE Jun-wei. Large capacity FLASH video storage controller base on blanking period of line and field signals[J]. Editorial Office of Optics and Precision Engineering, 2015,23(4): 1153-1160 DOI： 10.3788/OPE.20152304.1153.

摘要

为克服传统大容量FLASH视频存储控制器时序设计复杂、缓存资源要求较高的缺点

设计了一种利用视频行场信号消隐期进行时序控制的FLASH视频存储控制器。该控制器基于FPGA时序设计

利用视频行场同步信号消隐期时间写入FLASH的读出和写入控制命令。由于无需缓存资源即可实现多级流水线的设计

提高了时序控制效率

简化了时序设计过程。基于Verilog 硬件描述语言

设计了3级流水线和并行控制时序

数据达120 MB/s

实现了对2 048 pixel×1 752 pixel/15 frames高速视频数据的实时存储与回放。仿真与实验结果均表明

系统时序设计正确

大容量FLASH阵列读写操作正常

可实现视频数据的采集、存储、回放等多种功能。

Abstract

A FLASH video storage controller using the blanking period of line and field signals to control time sequence was designed to overcome the disadvantages of complex timing design and large cache resource requirements of traditional ones. The controller was designed based on the Field Programming Gate Array(FPGA) and its reading and writing control commands were input FLASH by line and field signals on the blanking period. In this way

the multistage pipeline could be implemented without cache resources

design control timing was greatly simplified and cache resources were saved. Additionally

a three-stage pipeline was designed based on the Verilog software describing language

which realizes the real-time storage and playback of 2048 pixel×1752 pixel/15 frames in high speed video data with the throughput rate as high as 120 MB/s. Simulation and experiment results show that the system timing design is correct

and large capacity FLASH array reading and writing operation is right. The design can accomplish multifunction operations such as real-time control

storage and the playback of high speed video data.

关键词

Keywords

references

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Related Institution

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Graduate University of Chinese Academy of Sciences, Beijing 100039, China

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