Design of signal processing module for infrared focal plane detector

GE Jun; WANG Xiao; REN Yue-min

doi:10.3788/OPE.20172513.0281

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Design of signal processing module for infrared focal plane detector

更新时间：2020-08-13

- Design of signal processing module for infrared focal plane detector
- Optics and Precision Engineering Vol. 25, Issue 10s, Pages: 281-287(2017)
- 作者机构：
  
  中国科学院上海技术物理研究所红外物理国家重点实验室红外探测与成像技术重点实验室, 上海 200083
- 作者简介：
- 基金信息：
- DOI：10.3788/OPE.20172513.0281
  CLC： TP752.1
- Received：10 July 2017，
  
  Revised：27 July 2017，
  
  Published：25 November 2017
- 稿件说明：
移动端阅览
葛军, 汪晓, 任月敏. 红外焦平面探测器信号处理模块设计[J]. 光学精密工程, 2017,25(10s): 281-287

GE Jun, WANG Xiao, REN Yue-min. Design of signal processing module for infrared focal plane detector[J]. Editorial Office of Optics and Precision Engineering, 2017,25(10s): 281-287
葛军, 汪晓, 任月敏. 红外焦平面探测器信号处理模块设计[J]. 光学精密工程, 2017,25(10s): 281-287 DOI： 10.3788/OPE.20172513.0281.

GE Jun, WANG Xiao, REN Yue-min. Design of signal processing module for infrared focal plane detector[J]. Editorial Office of Optics and Precision Engineering, 2017,25(10s): 281-287 DOI： 10.3788/OPE.20172513.0281.

摘要

针对基于场景的神经网络非均匀性校正算法对硬件架构自身数据运算与传输能力要求较高的问题，为实现片上实时运算、高效数据处理等目标，选取了Kintex7系列的XC7K325T FPGA和TI C66x系列TMS320C6657 DSP芯片，搭建了基于FPGA和双核DSP架构的信号处理模块。在设计中引入了高速率DDR3来提高系统整体数据吞吐能力，并利用SRIO接口技术设计并实现了FPGA和DSP之间的数据互连，达到了2.5 Gb/s的理论传输速率。同时，在DSP处理芯片内部实现了神经网络非均匀性校正算法逻辑，片上实时计算校正参数矩阵，在640×512分辨率红外探测器连续50 h工作的模式下稳定运行。最终，集成模块最大单板面积为90 mm×52 mm，整个模块综合高度低于50 mm，红外图像输出非均匀性稳定低于0.1%，满足了小型化、实时性的信号处理模块设计需求并达到了工程标准。

Abstract

Aimed at theneural network non-uniformity correction algorithm based on scenes requires high standards on hardware architecture data operation and transmission capacity

in order to achieve on-chip real-time operation

high-efficient data processing and other purposes

XC7K325T FPGA chip of Kintex 7 series and TMS320C6657 DSP chip of TI C66x series were adopted to construct signal processing module based on FPGA and dual-core DSP architecture. DDR3 with high speed was introduced in the design to improve overall system data throughput capacity

statistical interconnection between FPGA and DSP was designed and achieved by using SRIO interface technology

and theoretical transmission speed of 2.5 Gb/s was reached. At the same time

algorithm logic of neural network non-uniformity correction was realized in the interior of DSP processing chips

correction parameter matrix was calculated in real time on the chips

and stable operation was implemented under the mode of continuous work for 50 H of infrared detector with resolution ratio of 640×512. Finally

maximum single board area of integrated module is 90 mm×52 mm

integrated height of the whole module is less than 50 mm and stability of non-uniformity of infrared image output is less than 0.1%

which satisfies miniaturized and real-time design demands of signal processing module

and achieves engineering standard.

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references

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