In order to reduce the power consumption of image fusion system based on FPGA

the main factors impacting on the system power consumption were introduced. Then the low power designs of main modules in the system were analyzed in detail

including power module

outer memorizer

FPGA device and so on. The Virtex-4 SX35 FPGA equaling to a device of three million logic gates produced by Xilinx for high-performance signal processing was selected

and TPS54310 and TPS54610 with low power character

and adjustable output voltage of 0.9~3.3 V and accuracy of 1% designed by TI were used to produce the main system power. ZBT SRAM was chosen for outer memorizer to realize unlimited true back-to-back read/write operations without waiting states

it can dramatically improve the throughput of data in system

especially when it requires write/read transitions frequently. With the characteristics of fusion algorithms and the advantages in resource and technology of Virtex-4 FPGAs

the particular low power design was discussed around such techniques as bus coding

pipeline design and parallel processing

etc. The analytic conclusions indicate that the real power consumption of the system can be reduced effectively and its reliability can be guaranteed if the foregoing designs are adopted properly.