In order to realize the optic-electronic detection precisely

the increase of FFT computing speed is the main subject in these detection systems and that parallel computing and pipeline structure are the basic technologies to achieve high speed of large scale FFT computing. The FFT processor is a hybrid architectures including parallel processing and SDF (single—path delay feedback) pipeline based on FPGA chip. The memory cost of the processor decreased compared with the full parallel architecture while the speed is higher than the SDF pipeline architecture. The algorithm and design model for the processor was established and the three modules of the processor according to the design model were optimized to decrease resource cost greatly while the speed is higher than generous pipeline architectures．Verified with the FPGA simulations and hardware circuits’ platform in lab

the results show that the design achieves the operating frequency at 150MHz and the data throughout exceed 600 Msps.