闭环电容式微加速度计全差分CMOS接口电路

刘晓为; 尹亮; 李海涛; 周治平

doi:10.3788/OPE.20111903.0580

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闭环电容式微加速度计全差分CMOS接口电路

微纳技术与精密机械 | 更新时间：2020-08-12

- 闭环电容式微加速度计全差分CMOS接口电路
- Full differential CMOS interface circuit for closed-loop capacitive micro-accelerometers
- 光学精密工程 2011年19卷第3期页码：580-586
- 作者机构：
  
  哈尔滨工业大学微电子技术与科学系,黑龙江哈尔滨,150001
- 作者简介：
- 基金信息：
  
  国家863高技术研究发展计划资助项目(No.2008AA04220)()
- DOI：10.3788/OPE.20111903.0580
  中图分类号： TH824.4;TN432
- 收稿日期：2010-06-04，
  
  修回日期：2010-08-17，
  
  网络出版日期：2011-03-22，
  
  纸质出版日期：2011-03-22
- 稿件说明：
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刘晓为, 尹亮, 李海涛, 周治平. 闭环电容式微加速度计全差分CMOS接口电路[J]. 光学精密工程, 2011,19(3): 580-586

LIU Xiao-wei, YIN Liang, LI Hai-tao, ZHOU Zhi-ping. Full differential CMOS interface circuit for closed-loop capacitive micro-accelerometers[J]. Editorial Office of Optics and Precision Engineering, 2011,19(3): 580-586
刘晓为, 尹亮, 李海涛, 周治平. 闭环电容式微加速度计全差分CMOS接口电路[J]. 光学精密工程, 2011,19(3): 580-586 DOI： 10.3788/OPE.20111903.0580.

LIU Xiao-wei, YIN Liang, LI Hai-tao, ZHOU Zhi-ping. Full differential CMOS interface circuit for closed-loop capacitive micro-accelerometers[J]. Editorial Office of Optics and Precision Engineering, 2011,19(3): 580-586 DOI： 10.3788/OPE.20111903.0580.

摘要

提出了一种用于电容式微加速度计的低噪声、高线性度全差分接口电路。基于开关电容检测技术

该电路采用一种新的双路反馈结构来提高系统线性度

并采用2 m

阱CMOS工艺完成芯片设计。仿真结果证明

电路中采用的双路反馈和全差分检测结构使系统的线性度达到0.01%。加入经过优化设计的比例-微分-积分控制器后

有效减小了系统稳态误差

系统响应速度提高了31%

系统线性度提高了66.7%。在5 V工作电压下

选取64 kHz作为电路采样频率时

其电路等效输入噪声为8

-1/2

系统灵敏度为1.22 V/

线性度为0.03%

测量范围为2

。测试结果显示

提出的电路达到高精度微加速度计系统设计要求

可以应用到地震监测、石油勘探等领域中。

Abstract

A CMOS full differential interface circuit with low noise and high linearity was presented for closed-loop capacitive micro-accelerometers. Based on switched-capacitor detection

the circuit was designed to improve its linearity by a 0.5 m n-well CMOS process technology. The simulation result shows that the proposed two-path feedback structure provides a good system linearity of 0.01%. The optimized designed PID controller was added into the system

which decreases the stabilization error effectively

increases the system responding speed by 31%

and the linearity by 66.7%. With a 5 V supply and a sampling frequency of 64 kHz

the circuit can offer the equivalent input noise in 8

-1/2

system sensitivity in 1.22 V/g

system linearity in 0.03%

and the work range in 2

. These results prove that this circuit is suitable for applications of high performance micro-accelerometers to seism detection

oil exploration

etc

关键词

Keywords

references

K LAH H, CHAE J, YAZDI N, et al.. Noise analysis and characterization of a sigma-delta capacitive microaccelerometer [J]. IEEE Journal of Solid-State Circuits, 2006,41(2):352-361.[2] AALTONEN L,HALONEN K. Continuous-time interface for a micromachined capacitive accelerometer with NEA of 4 g and bandwidth of 300 Hz [J]. Sensors and Actuators A, 2009,154:46-56.[3] LEE W F, CHAN P K. A capacitive-based accelerometer IC using injection-nulling switch technique [J]. IEEE Transactions on Circuits and Systems I, 2008,55(4):980-989.[4] TAN X Y, ZHOU X ZH, XU N, et al.. Error analysis on numerical double integration in acceleration measurement with clock jitter [J]. Opt. Precision Eng., 2009,17(7):1630-1634.[5] YIN L, CHEN W P, LIU X W,et al.. CMOS interface circuit for closed-loop accelerometer [J]. Opt. Precision Eng., 2009,17(6):1311-1315.[6] AMINI B V, AYAZI F. A 2.5V 14-bit sigma-delta CMOS-SOI capacitive accelerometer [J]. IEEE Journal of Solid State Circuits, 2004,39(12):2467-2476.[7] LIU Y T, YIN L, CHEN W P, et al. Design of interface circuit of closed-loop accelerometer with self-test function [J]. Opt. Precision Eng., 2009,17(6):1379-1385.[8] BANU M, KHOURY J M , TSIVIDIS Y. Fully differential operational amplifiers with accurate output balancing [J]. IEEE Journal of Solid-State Circuits, 1988,23(6):1410-1414.[9] SANSEN W M C. Analog design essentials [M]. 陈莹梅,译. 北京: 清华大学出版社, 2008.[10] K LAH H, YAZDI N, NAJAFI K. A CMOS switched-capacitor interface circuit for an integrated accelerometer . Proceedings of 43rd IEEE Midwest Symposium on Circuits and Systems, Lansing, 2000:244-247.[11] BASCHIROTTO A, GOLA A, CHIESA E, et al.. A 1 g dual axis linear accelerometer in a standard 0.5 m CMOS technology for high-sensitivity applications [J]. IEEE Journal of Solid-State Circuits, 2003, 38(7):1292-1297.[12] WU J, FEEDER G K, CARLEY L R. A low-noise low-offset capacitive sensing amplifier for a 50 g/ Hz monolithic CMOS MEMS accelerometer [J]. IEEE Journal of Solid-State Circuits, 2004,39(5):722-730.[13] PETKOV V P, BOSER B E. A fourth-order interface for micromachined inertial sensors [J]. IEEE Journal of Solid-State Circuits, 2005,40(8):1602-1609.[14] LEE W F,CHAN P K. A capacitive-based accelerometer IC using Injection-Nulling Switch Technique [J]. IEEE Transactions on circuits and systems I. 2008,55(4):980-989.

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