应用聚类和粗糙集的FPGA底层数据挖掘方法

姜大力; 赵波; 常亮; 李华旺; 杨根庆

doi:10.3788/OPE.20132101.0233

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应用聚类和粗糙集的FPGA底层数据挖掘方法

信息科学 | 更新时间：2020-08-12

- 应用聚类和粗糙集的FPGA底层数据挖掘方法
- FPGA low level data mining approach based on cluster and rough set
- 光学精密工程 2013年21卷第1期页码：233-238
- 作者机构：
  
  中国科学院上海微系统与信息技术研究所2. 中国科学院长春光学精密机械与物理研究所3 中国科学院大学
- 作者简介：
- 基金信息：
  
  空间科学战略性先导科技专项资金资助项目（No.XD04040202）()
- DOI：10.3788/OPE.20132101.0233
  中图分类号： TP302.8
- 收稿日期：2012-03-14，
  
  修回日期：2012-04-19，
  
  网络出版日期：2013-01-24，
  
  纸质出版日期：2013-01-15
- 稿件说明：
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姜大力赵波常亮李华旺杨根庆. 应用聚类和粗糙集的FPGA底层数据挖掘方法[J]. 光学精密工程, 2013,21(1): 233-238

JIANG Da-li ZHAO Bo CHANG Liang LI Hua-wang YANG Gen-qing. FPGA low level data mining approach based on cluster and rough set[J]. Editorial Office of Optics and Precision Engineering, 2013,21(1): 233-238
姜大力赵波常亮李华旺杨根庆. 应用聚类和粗糙集的FPGA底层数据挖掘方法[J]. 光学精密工程, 2013,21(1): 233-238 DOI： 10.3788/OPE.20132101.0233.

JIANG Da-li ZHAO Bo CHANG Liang LI Hua-wang YANG Gen-qing. FPGA low level data mining approach based on cluster and rough set[J]. Editorial Office of Optics and Precision Engineering, 2013,21(1): 233-238 DOI： 10.3788/OPE.20132101.0233.

摘要

提出了一种从XDL文件中提取现场可编程门阵列(FPGA)底层逻辑和布线资源的方法。预处理阶段通过正则表达式将原有底层逻辑文件转换为待分析的有层次属性的关系型数据库。数据挖掘阶段则根据各个层次数据内部的特性不同，采用不同的算法进行聚类来得到初步知识。通过粗糙集分析初步知识间的关系和约简属性，得出初步知识间的联系同时进一步提取出决策规则和产生式规则的知识。最后，通过规则验证器和泛化器对提取出的规则进行验证和泛化。实验结果表明，对于大型的FPGA器件，wire的逻辑最高压缩比可以达到2.8810-4。该方法相对于底层器件有较好的通用性和交互性，适用于对不同器件族FPGA底层信息的知识提取

对深入研究FPGA的拓扑架构

提高对FPGA进行动态重配置的可控性和实现更灵活的重配置很有意义。

Abstract

This paper provides a method to get low level logic and route resources of a Field Programming Gate Array(FPGA) from XDL documents. In the preprocess stage

the lowly logic document is transformed to a relational database with different attributes via a regular expression. In the data mining stage

different algorithms are adopted to cluster the data to get preliminary knowledge based on the different internal features of each level of the database. By taking a rough set to analyze the preliminary knowledge and summarize its attribute

the relation of the preliminary knowledge is obtained and the knowledge for decision rule and production rule is given. Finally

the above rules are validated and generalized through a validator and a generalization device. Experiments show that the highest compressing rate of wire logic can reach 2.8810-4 for a huge FPGA. This method has good versatility and interchangeability and is suitable for acquiring the low level information and knowledge from FPGAs in different apparatus families. The method has signification in exploring the topology framework of FPGA

improving controllability for dynamic reconfiguration of FPGA

and achieving more flexibility reconfiguration.

关键词

Keywords

references

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