流水线模拟数字转换器的权重误差校准

贾华宇; 刘丽; 张建国

doi:10.3788/OPE.20142211.3114

您当前的位置：

首页 >

文章列表页 >

流水线模拟数字转换器的权重误差校准

信息科学 | 更新时间：2020-08-13

- 流水线模拟数字转换器的权重误差校准
- Calibration of weight-error for pipelined ADCs
- 光学精密工程 2014年22卷第11期页码：3114-3121
- 作者机构：
  
  太原理工大学新型传感器与智能控制教育部重点实验室,山西太原,030024
- 作者简介：
- 基金信息：
  
  null()
- DOI：10.3788/OPE.20142211.3114
  中图分类号： TN792
- 收稿日期：2014-06-27，
  
  修回日期：2014-08-25，
  
  纸质出版日期：2014-11-25
- 稿件说明：
移动端阅览
贾华宇, 刘丽, 张建国. 流水线模拟数字转换器的权重误差校准[J]. 光学精密工程, 2014,22(11): 3114-3121

JIA Hua-yu, LIU Li, ZHANG Jian-guo. Calibration of weight-error for pipelined ADCs[J]. Editorial Office of Optics and Precision Engineering, 2014,22(11): 3114-3121
贾华宇, 刘丽, 张建国. 流水线模拟数字转换器的权重误差校准[J]. 光学精密工程, 2014,22(11): 3114-3121 DOI： 10.3788/OPE.20142211.3114.

JIA Hua-yu, LIU Li, ZHANG Jian-guo. Calibration of weight-error for pipelined ADCs[J]. Editorial Office of Optics and Precision Engineering, 2014,22(11): 3114-3121 DOI： 10.3788/OPE.20142211.3114.

摘要

为校准流水线模拟数字转换器(ADC)中电容失配和由运算放大器的有限开环增益引起的级间增益误差

提出了一种新的基于权重的后台校准技术。该技术将流水线ADC中存在的上述误差统一归结为各级权重的偏差

建立了一个基于权重的ADC误差模型

并利用后级的数字输出来校准前级的误差。该技术在ADC末尾增加了额外的两个子级

这两个子级仅在校准过程中使用

从而使得ADC正常的模数转换过程不被中断

校准进程在后台执行。由于在校准期间和正常工作期间所有可能出现的信号路径的前7级均被校准

故进一步减小了误差

提高了精度。应用该技术实现了一个14 bit

80 MS/s的流水线ADC

该芯片采用Chartered 0.18 m

1p6m CMOS工艺设计

总功耗为260 mW

芯片面积为7.161 mm

。实验结果显示:本文提出的校准技术可以提高ADC的精度

改善ADC的动态和静态性能。

Abstract

To reduce and eliminate the interstage gain errors caused by capacitor mismatch and finite open-loop gain of an operating amplifier in a pipelined Analog to Digital Converter (ADC)

a novel weight-based calibration technique on backend stages was presented. With proposed technique

a weight-based error model was built by merging error factors into a single term and the outputs of backend stages were utilized to calibrate the errors of front stages. To avoid interrupt normal conversion process

two extra stages were used in the calibration process to implement background calibration. During the normal conversion process and calibration process

the first seven stages of every signal path were all calibrated to increase the resolution and to eliminate errors. The improved technique was used in the implementation of 14 b

80 MS/s pipelined ADC

and the ADC is with Chartered 0.18 m

1p6m CMOS process

a consume of 260 mW

and a chip area of 7.161 mm

. The test results show that the calibration technique improves dynamic and static performance and increases the precisions of pipelined ADCs.

关键词

Keywords

references

张晞,李德燕,王洪波,等. 数字闭环加速度计的带宽测试[J]. 光学精密工程,2014,22(1): 92-98. ZHANG X, LI D Y, WANG H B. Bandwidth measurement of digital closed-looop accelerometer[J]. Opt. Precision Eng., 2014, 22(1): 92-98. (in Chinese)

赵慧洁,刘小康,张颖. 声光可调谐滤波成像光谱仪的CCD成像电子学系统[J]. 光学精密工程,2013,21(5): 1291-1296. ZHAO H J, LIU X K, ZHANG Y. CCD imaging electrical system of AOTF imaging spectrometer[J]. Opt. Precision Eng., 2013, 21(5): 1291-1296. (in Chinese)

AMICO S D, COCCIOLO G, SPAGNOLO A, et al.. A 7.65-mW 5-bit 90-nm 1-Gs/s folded Interpolated ADC without calibration[J]. IEEE Transactions on Instrumentation and Measurement, 2014, 63(2):295-303.

FANG B N, WU J T. A 10-Bit 300-MS/s pipelined ADC with digital calibration and digital bias generation[J]. IEEE Journal of Solid-State Circuits, 2013, 48(3): 670-683.

袁博宇,李威,罗成名. 溶液浓度变化实时检测系统的设计[J]. 光学精密工程,2014,22(1): 18-23. YUAN B Y, LI W, LUO CH M. Design of real-time measurement system for solution concentration changes[J]. Opt. Precision Eng., 2014, 22(1): 18-23. (in Chinese)

陈健,高慧斌,郭劲,等. 数字化单杆控制系统设计[J]. 光学精密工程,2013,21(11): 2844-2851. CHEN J, GAO H B, GUO J. Design of digital handle control system[J]. Opt. Precision Eng., 2013, 21(11): 2844-2851. (in Chinese)

XIONG ZH X, CAI M, HE X Y. Digital background calibration for A 14-bit 100-MS/s pipelined ADC using signal-dependent dithering[C]. Proceedings of IEEE International Conference of Electron Devices and Solid-State Circuits, Hong Kong, China, EDSSC, 2013: 1-2.

MATSUNO J, YAMAJI T, FURUTA M, et al.. All-digital background calibration technique for time-interleaved ADC using pseudo aliasing signal[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2013, 60(5): 1113-1121.

KARANICOLAS A N, HAE-SEUNG L, BARCRANIA K L. A 15-b 1-Msample/s digitally self-calibrated pipeline ADC[J]. IEEE Journal of Solid-State Circuits, 1993, 28(12): 1207-1215.

DELIC-IBUKIC A, HUMMELS D M. Continuous digital calibration of pipeline A/D converters[J]. IEEE Transactions on Instrumentation and Measurement,2006, 55(4):1175-1185.

GUSTAVSSON M, WIKNER J J, TAN N N. CMOS Data Converters for Communications[M]. Boston: Kluwer Academic Publishers, 2000.

YOUNG-JAE C, KYUNG-HOON L, HEE-CHEOL C, et al.. A Calibration-Free 14b 70MS/s 3.3 mm 2 235 mW 0.13 μm CMOS pipeline ADC with high-matching 3-D symmetric capacitors[C]. Custom Integrated Circuits Conference, San Jose, USA, 2006: 485-488.

浏览量

420

下载量

CSCD

文章被引用时，请邮件提醒。

提交

工具集

关联资源

暂无数据