节约器件的三维离散余弦正/反变换通道式算法结构

刘媛媛; 陈贺新; 赵岩

doi:10.3788/OPE.20152311.3270

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节约器件的三维离散余弦正/反变换通道式算法结构

信息科学 | 更新时间：2020-08-13

- 节约器件的三维离散余弦正/反变换通道式算法结构
- Pipeline architectures of device-saving three dimensional DCT/IDCT algorithm
- 光学精密工程 2015年23卷第11期页码：3270-3278
- 作者机构：
  
  1. 吉林大学通信工程学院,吉林长春,中国,130012
  2. 吉林农业大学信息技术学院,吉林长春,130118
- 作者简介：
- 基金信息：
  
  国家自然科学基金资助项目(No.61171078, No.61271315)()
- DOI：10.3788/OPE.20152311.3270
  中图分类号： TN919
- 收稿日期：2015-09-01，
  
  修回日期：2015-09-29，
  
  纸质出版日期：2015-11-25
- 稿件说明：
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刘媛媛, 陈贺新, 赵岩. 节约器件的三维离散余弦正/反变换通道式算法结构[J]. 光学精密工程, 2015,23(11): 3270-3278

LIU Yuan-yuan, CHEN He-xin, ZHAO Yan. Pipeline architectures of device-saving three dimensional DCT/IDCT algorithm[J]. Editorial Office of Optics and Precision Engineering, 2015,23(11): 3270-3278
刘媛媛, 陈贺新, 赵岩. 节约器件的三维离散余弦正/反变换通道式算法结构[J]. 光学精密工程, 2015,23(11): 3270-3278 DOI： 10.3788/OPE.20152311.3270.

LIU Yuan-yuan, CHEN He-xin, ZHAO Yan. Pipeline architectures of device-saving three dimensional DCT/IDCT algorithm[J]. Editorial Office of Optics and Precision Engineering, 2015,23(11): 3270-3278 DOI： 10.3788/OPE.20152311.3270.

摘要

针对3D离散余弦正/反变换(DCT/IDCT)算法单元通道式结构需大量使用延时器和选择器以及不同分块器件的兼容性问题

提出一种节约延时器和选择器的通用性通道式算法单元及整体结构。首先

根据三维DCT理论提出兼容正反变换通用的通道式算法结构;建立由延时器和选择器组成的可重复使用的延时器组模型

使其具有整合性和嵌套性。然后

提出节约延时器的三维DCT通用性通道式算法单元及整体结构。最后

利用提出的节约器件的三维DCT/IDCT通道式结构对不同格式、不同大小分块的视频信号进行处理。实验结果表明

随着分块增大

提出的节约器件的方法使用的延时器和选择器的数量明显减小

当分块大小达到64×64×64时

延时器和选择器使用个数分别降低了54.7%和44.5%。得到的结果说明提出的方法可以减少延时器和选择器的使用

满足硬件对降低成本的要求

提高了能效

同时便于不同分块的集成。

Abstract

The general pipeline architecture units and corresponding structures were proposed. It overcomes the problems that the hardware architectures consisting of delayers

selectors and multiplying units based on 3D DCT/IDCT(Discrete Cosine Transform and Inverse Discrete Cosine Transform) should use a lot of devices independently and their different blocks are not easy to be integrated. Firstly

based on the theory of 3D DCT

universal pipeline algorithm architectures compatible with positive and negative transformations were proposed. The delayer-group models by reusing delayers and selectors were set up to allow the models to be integrative and nested. Then

unit device-saving pipeline architectures and the corresponding whole pipeline architecture of 3D DCT were proposed. Finally

video signals with different formats and size blocks were processed by using this device-saving 3D DCT/IDCT pipeline architectures proposed. The experimental results indicate that the reduce ratio of number of delayers and selectors increases obviously as block size increasing by using our device-saving algorithm. When the block size reaches 64×64×64

the used number of delayers and selectors reduce by 54.7% and 44.5% respectively. It shows that the proposed method reduces the used number of delayers and selectors

meets the demand of the hardware requirements for reducing costs

improves the energy efficiency

and facilitates the integration of different block sizes.

关键词

Keywords

references

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