The design problem of the high-speed RS decoder is discussed. The presentation of the finite-field elements in WDB is studied. And based on the computing method for the optimum WDB

the design for the bit parallel multiplier of finite-field is presented. By selecting the bit-parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion

the widely used RS decoder is constructed. The analysis results indicates: the complexity of the bit-parallel multiplier is low and is suited for VLSI implementation; the modified BM iterative algorithm makes the simple hardware implementation possible and is advantageous to On-The-Fly error correcting. The throughout of the decoder can reach a high value and it is suited for the high speed application.